1. Field of the Invention
The present invention relates to a clock generator and a clock generating method for generating a frequency divided clock signal with the same period as an input clock signal or frequency multiplied clock signal.
2. Description of Related Art
FIG. 10 shows a configuration of a conventional clock generator disclosed in Technical report of the Institute of electronics, information and communication engineers of Japan, pp. 29-36, Vol. 97, No. 106, published June, 1997, which is incorporated here by reference. In FIG. 10, the reference numeral 1 designates a frequency multiplier for generating a frequency multiplied clock signal by frequency multiplying an input clock signal; 2 designates a ring oscillator consisting of a digital delay line 3 for delaying the frequency multiplied clock signal; 3 designates the digital delay line of the ring oscillator 2; 4 designates a counter for setting a delay time of the digital delay line 3; 5 designates a phase comparator for comparing the phase of the input clock signal with that of a feedback clock signal output from a driver 9, and updates the counter value of a counter 7 in accordance with the phase difference; 6 designates a phase lock circuit for synchronizing the phase of the feedback clock signal with that of the input clock signal by delaying the frequency multiplied clock signal generated, and produces the delayed frequency multiplied clock signal as a PLL (phase-locked loop) output; 7 designates the counter of the phase lock circuit 6; 8 designates a digital delay line for delaying the frequency multiplied clock signal generated by the frequency multiplier 1 by a delay time corresponding to the counter value, the digital delay line 8 being composed of a plurality of delay elements and a decoder. The reference numeral 9 designates the driver for supplying the phase comparator 5 with the PLL output as the feedback clock signal; and each reference numeral 10 designates a driver for delivering to respective blocks the PLL output produced by the phase lock circuit 6.
Next, the operation of the conventional clock generator will be described.
First, the clock generator, which will be called "PLL (phase-locked loop)" from now on, generates a clock signal with the same cycle as the input clock signal or a frequency multiplied clock signal thereof, both of which are synchronized with the input clock signal. It is essential for modern microprocessors to include a PLL because they operate at a very high frequency in a range from a few tens to several hundred megahertz.
Conventional PLLs are an analog type PLL that controls its oscillation frequency by controlling with a charge pump the voltage of a capacitor which holds the control voltage of a voltage controlled oscillator (VCO).
The analog PLL, however, has problems of being not easy to control at a low voltage, susceptible to noise, and requiring a rather long time to re-operate once it has suspended its oscillation in response to the halt of the input clock signal, because it takes a long time (lock time) until its operation becomes stable.
To solve these problems, the conventional example as shown in FIG. 10 employs the digital delay lines to construct the PLL. More specifically, when the PLL receives the input clock signal, the digital delay line 3 of the frequency multiplier 1 multiplies the frequency of the input clock signal, and supplies it to respective blocks. Since the frequency multiplied clock signal, which is generated as the PLL output, must be synchronized with the input clock signal in their phases, the phase comparator 5 and phase lock circuit 6 carry out the following phase locking processing.
First, the phase comparator 5 compares the phase of the frequency multiplied clock signal which is generated by the frequency multiplier 1 with that of the feedback clock signal (corresponding to the PLL output) which is output from the driver 9, and makes a decision as to whether the phase difference is within an acceptable range.
If the phase difference is in the acceptable range, the phase lock circuit 6 decides that the phase of the frequency multiplied clock signal agrees with that of the input clock signal, and maintains the counter value of the counter 7 in the phase lock circuit 6, thereby keeping the delay time of the phase lock circuit 6. On the contrary, if the phase difference is out of the acceptable range, the phase lock circuit 6 judges that the phase of the frequency multiplied clock signal disagrees with that of the input clock signal, and updates (that is, increments or decrements) the counter value of the counter 7 in accordance with the phase difference, thereby controlling the delay time of the phase lock circuit 6.
When the counter value of the counter 7 is set in this way, the digital delay line 8 in the phase lock circuit 6 delays the frequency multiplied clock signal in accordance with the counter value of the counter 7, and supplies the delayed frequency multiplied clock signal to the drivers 9 and 10 as the PLL output. In this case, the digital delay line 8 delays the rising edge of a pulse of the frequency multiplied clock signal, which is immediately previous to the rising edge of each pulse of the input clock signal as shown in FIG. 11, so that the rising edge of the corresponding pulse of the feedback clock signal is synchronized with the rising edge of each pulse of the input clock signal.
Accordingly, the maximum delay time of the digital delay line 8 corresponds to one cycle of the frequency multiplied clock signal, and that of the digital delay line 3 constituting the ring oscillator 2 of the frequency multiplier 1 corresponds to half the cycle of the frequency multiplied clock signal.
Thus, the maximum delay time of the digital delay line 8 depends on the period of the frequency multiplied clock signal. For example, to generate the PLL output with a multiplication number of one (that is, the PLL output with a period equal to the period of the input clock signal) in order to save power, the maximum delay time of the digital delay line 8 becomes equal to the period of the PLL output. Therefore, the number of delay elements of the digital delay line 8 required in this case becomes four times that required when the multiplication number is four as illustrated in FIG. 11.
With such an arrangement, the conventional clock generator must lengthen the maximum delay time of the digital delay line 8 by an amount corresponding to the reduction in the multiplication number of the frequency multiplied clock signal, which requires an increasing number of delay elements and a decoder. Since the delay elements and the decoder occupy a rather large area, the reduction of the multiplication number of the frequency multiplied clock signal presents a problem of increasing the scale of the circuit, incurring an increase in the cost of the chip in some cases.
Furthermore, since the multiplication number of the frequency multiplied clock signal is usually fixed, it cannot be easily changed once the chip has been built.